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| Features * * * * * * * * * * * * * * 26-42 MIPS Integer Performance 3.5-5.6 MFLOPS Floating-Point-Performance IEEE 754-Compatible FPU Independent Instruction and Data MMUs 4K bytes Physical Instruction Cache and 4K bytes Physical Data Cache Accessed Simultaneously 32-bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface User-Object-Code Compatibility with All Earlier TS68000 Microprocessors Multimaster/Multiprocessor Support via Bus Snooping Concurrent Integer Unit, FPU, MMU, Bus Controller, and Bus Snooper Maximize Throughput 4G bytes Direct Addressing Range Software Support Including Optimizing C Compiler and UNIX(R) System V Port IEEE P 1149-1 Test Mode (JTAG) f = 25 MHz, 33 MHz; VCC = 5V 5%; PD = 7W The Use of the TS88915T Clock Driver is Suggested ThirdGeneration 32-bit Microprocessor TS68040 Description The TS68040 is Atmel's third generation of 68000-compatible, high-performance, 32bit microprocessors. The TS68040 is a virtual memory microprocessor employing multiple, concurrent execution units and a highly integrated architecture to provide very high performance in a monolithic HCMOS device. On a single chip, the TS68040 integrates a 68030-compatible integer unit, an IEEE 754-compatible floating-point unit (FPU), and fully independent instruction and data demand-paged memory management units (MMUs), including 4K bytes independent instruction and data caches. A high degree of instruction execution parallelism is achieved through the use of multiple independent execution pipelines, multiple internal buses, and a full internal Harvard architecture, including separate physical caches for both instruction and data accesses. The TS68040 also directly supports cache coherency in multimaster applications with dedicated on-chip bus snooping logic. The TS68040 is user-object-code compatible with previous members of the TS68000 Family and is specifically optimized to reduce the execution time of compiler-generated code. The 68040 HCMOS technology, provides an ideal balance between speed, power, and physical device size. Figure 1 is a simplified block diagram of the TS68040. Instruction execution is pipelined in both the integer unit and FPU. Independent data and instruction MMUs control the main caches and the address translation caches (ATCs). The ATCs speed up logical-to-physical address translations by storing recently used translations. The bus snooper circuit ensures cache coherency in multimaster and multiprocessing applications. Screening * * * MIL-STD-883 DESC. Drawing 5962-93143 Atmel Standards Rev. 2116A-HIREL-09/02 1 R suffix PGA 179 Ceramic Pin Grid Array Cavity Down F suffix CQFP 196 Gullwing Shape Lead Ceramic Quad Fla Pack Figure 1. Block Diagram INSTRUCTION DATA BUS INSTRUCTION ATC INSTRUCTION CACHE INSTRUCTION ADDRESS INSTRUCTION FETCH CONVERT DECODE EFFECTIVE ADDRESS CALCULATE EFFECTIVE ADDRESS FETCH EXECUTE WRITE BACK WRITE BACK INSTRUCTION MMU/CACHE/SNOOP CONTROLLER INSTRUCTION MEMORY UNIT B U S C O N T R O L L E R ADDRESS BUS EXECUTE DATA BUS DATA MEMORY UNIT DATA MMU/CACHE/SNOOP CONTROLLER DATA ADDRESS BUS CONTROL SIGNALS FLOATINGPOINT UNIT INTEGER UNIT DATA ATC DATA CACHE OPERAND DATA BUS 2 TS68040 2116A-HIREL-09/02 TS68040 Introduction The TS68040 is an enhanced, 32-bit, HCMOS microprocessor that combines the integer unit processing capabilities of the TS68030 microprocessor with independent 4K bytes data and instruction caches and an on-chip FPU. The TS68040 maintains the 32-bit registers available with the entire TS68000 Family as well as the 32-bit address and data paths, rich instruction set, and versatile addressing modes. Instruction execution proceeds in parallel with accesses to the internal caches, MMU operations, and bus controller activity. Additionally, the integer unit is optimized for high-level language environments. The TS68040 FPU is user-object-code compatible with the TS68882 floating-point coprocessor and conforms to the ANSI/IEEE Standard 754 for binary floating-point arithmetic. The FPU has been optimized to execute the most commonly used subset of the TS68882 instruction set, and includes additional instruction formats for single and double-precision rounding of results. Floating-point instructions in the FPU execute concurrently with integer instructions in the integer unit. The MMUs support multiprocessing, virtual memory systems by translating logical addresses to physical addresses using translation tables stored in memory. The MMUs store recently used address mappings in two separate ATCs-on-chip. When an ATC contains the physical address for a bus cycle requested by the processor, a translation table search is avoided and the physical address is supplied immediately, incurring no delay for address translation. Each MMU has two transparent translation registers available that define a one-to-one mapping for address space segments ranging in size from 16M bytes to 4G bytes each. Each MMU provides read-only and supervisor-only protections on a page basis. Also, processes can be given isolated address spaces by assigning each a unique table structure and updating the root pointer upon a task swap. Isolated address spaces protect the integrity of independent processes. The instruction and data caches operate independently from the rest of the machine, storing information for fast access by the execution units. Each cache resides on its own internal address bus and internal data bus, allowing simultaneous access to both. The data cache provides write through or copyback write modes that can be configured on a page-by-page basis. The TS68040 bus controller supports a high-speed, non multiplexed, synchronous external bus interface, which allows the following transfer sizes: byte, word (2 bytes), long word (4 bytes), and line (16 bytes). Line accesses are performed using burst transfers for both reads and writes to provide high data transfer rates. 3 2116A-HIREL-09/02 Pin Assignments PGA 179 Figure 2. Bottom View Table 1. Power Supply Affectation to PGA Body GND PLL Internal Logic Output Drivers C6, C7, C9, C11,C13, K3, K16, L3, M16, R4, R11, R13, S10, T4, S9, R6, R10 B2, B4, B6, B8, B10, B13, B15, B17, D2, D17, F2, F17, H2, H17, L2, L17, N2, N17, Q2, Q17, S2, S15, S17 VCC S8 C5, C8, C10, C12, C14, H3, H16, J3, J16, L16, M3, R5, R12, R8 B5, B9, B14, C2, C17, G2, G17, M2, M17, R2, R17, S16 4 TS68040 2116A-HIREL-09/02 TS68040 CQFP 196 Figure 3. Pin Assignments Table 2. Power Supply Affectation to CQFP Body GND PLL Internal Logic Output Drivers 4, 9, 10, 19, 32, 45, 73, 88, 113, 119, 121, 122, 124, 125, 129, 130, 141, 159, 172 7, 15, 22, 28, 35, 42, 49, 50, 51, 57, 63, 69, 76, 77, 83, 84, 91, 97, 98, 99, 105, 106, 146, 147, 148, 149, 155, 162, 163, 169, 176, 182, 183, 189, 195, 196 VCC 127 3, 18, 31, 40, 46, 60, 72, 87, 114, 126, 137, 158, 173, 186 12, 25, 38, 54, 66, 80, 94, 102, 152, 166, 179, 192 5 2116A-HIREL-09/02 Signal Description Figure 4 and Table 3 describe the signals on the TS68040 and indicate signal functions. The test signals, TRST, TMS, TCK, TDI, and TDO, comply with subset P-1149.1 of the IEEE testability bus standard. Figure 4. Functional Signal Groups 6 TS68040 2116A-HIREL-09/02 TS68040 Table 3. Signal Index Signal Name Address Bus Data Bus Transfer Type Transfer Modifier Transfer Line Number User Programmable Attributes Read Write Transfer Size Bus Lock Bus Lock End Cache Inhibit Out Transfer Start Transfer in Progress Transfer Acknowledge Transfer Error Acknowledge Transfer Cache Inhibit Transfer Burst Inhibit Data Latch Enable Snoop Control Memory Inhibit Bus Request Bus Grant Bus Busy Cache Disable MMU Disable Reset In Reset Out Interrupt Priority Level Interrupt Pending Autovector Processor Status Mnemonic A31-A0 D31-D0 TT1, TT0 TM2, TM0 TLN1, TLN0 UPA1, UPA0 R/W SIZ1, SIZ0 LOCK LOCKE CIOUT TS TIP TA TEA TCI TBI DLE SC1, SC0 MI BR BG BB CDIS MDIS RSTI RSTO IPL2-IPL0 IPEND AVEC PST3-PST0 Function 32-bit address bus used to address any of 4G bytes 32-bit data bus used to transfer up to 32 bits of data per bus transfer Indicates the general transfer type: normal, MOVE 16, alternate logical function code, and acknowledge Indicates supplemental information about the access Indicates which cache line in a set is being pushed or loaded by the current line transfer User-defined signals, controlled by the corresponding user attribute bits from the address translation entry Identifies the transfer as a read or write Indicates the data transfer size. These signals, together with A0 and A1, define the active sections of the data bus Indicates a bus transfer is part of a read-modify-write operation, and that the sequence of transfers should not be interrupted Indicates the current transfer is the last in a locked sequence of transfer Indicates the processor will not cache the current bus transfer Indicates the beginning of a bus transfer Asserted for the duration of a bus transfer Asserted to acknowledge a bus transfer Indicates an error condition exists for a bus transfer Indicates the current bus transfer should not be cached Indicates the slave cannot handle a line burst access Alternate clock input used to latch input data when the processor is operating in DLE mode Indicates the snooping operation required during an alternate master access Inhibits memory devices from responding to an alternate master access during snooping operations Asserted by the processor to request bus mastership Asserted by an arbiter to grant bus mastership to the processor Asserted by the current bus master to indicate it has assumed ownership of the bus Dynamically disables the internal caches to assist emulator support Disables the translation mechanism of the MMUs Processor reset Asserted during execution of the RESET instruction to reset external devices Provides an encoded interrupt level to the processor Indicates an interrupt is pending Used during an interrupt acknowledge transfer to request internal generation of the vector number Indicates internal processor status 7 2116A-HIREL-09/02 Table 3. Signal Index (Continued) Signal Name Bus Clock Processor Clock Test Clock Test Mode Select Test Data Input Test Data Output Test Reset Power Supply Ground Mnemonic BCLK PCLK TCK TMS TDI TDO TRST VCC GND Function Clock input used to derive all bus signal timing Clock input used for internal logic timing. The PCLK frequency is exactly 2X the BCLK frequency Clock signal for the IEEE P1149.1 test access port (TAP) Selects the principle operations of the test-support circuitry Serial data input for the TAP Serial data output for the TAP Provides an asynchronous reset of the TAP controller Power supply Ground connection Scope This drawing describes the specific requirements for the microprocessor TS68040 25 MHz and 33 MHz, in compliance with MIL-STD-883 class B or Atmel standard screening. Applicable Documents MIL-STD-883 1. MIL-STD-883: test methods and procedures for electronics. 2. MIL-I-38535: general specifications for microcircuits. 3. DESC 5962-93143. Requirements General Design and Construction Terminal Connections Lead Material and Finish See Figure 2 and Figure 3. Lead material and finish shall be as specified in MIL-STD-883 (see enclosed "MIL-STD883 C and Internal Standard" on page 46). The macro circuits are packaged in hermetically sealed ceramic packages which conform to case outlines of MIL-STD-1835-or as follow: * * CMGA 10-179-PAK pin grid array, but see "179 pins - PGA" on page 43. Similar to CQCC1-F196C-U6 ceramic uniform lead chip carrier package with ceramic nonconductive tie-bar but use Atmel's internal drawing, see "196 pins - Tie Bar CQFP Cavity Up (on request)" on page 44. Gullwing shape CQFP see "196 pins - Gullwing CQFP cavity up" on page 45. The microcircuits are in accordance with the applicable document and as specified herein. Package * 8 TS68040 2116A-HIREL-09/02 TS68040 The precise case outlines are described at the end of the specification (See "Package Mechanical Data" on page 43.) and into MIL-STD-1835. Electrical Characteristics Absolute Maximum Ratings Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Condition Min -0.3 -0.3 Large buffers enabled PD TC Tstg TJ Note: Power Dissipation Small buffers enabled Operating Temperature Storage Temperature Range Junction Temperature (1) Table 4. Absolute Maximum Ratings Symbol VCC VI Parameter Supply Voltage Range Input Voltage Range Max 7.0 7.0 7.7 6.3 -55 -65 TJ +150 +125 Unit V V W W C C C Tlead Lead Temperature Max.10 sec soldering +300 C 1. This device is not tested at TC = +125C. Testing is performed by setting the junction temperature Tj = +125C and allowing the case and ambient temperatures to rise and fall as necessary so as not to exceed the maximum junction temperature. Table 5. Recommended Conditions of Use Unless otherwise stated, all voltages are referenced to the reference terminal Symbol VCC VIL VIH VOH VOL fc TC TJ Note: Case Operating Temperature Range Parameter Supply Voltage Range Logic Low Level Input Voltage Range Logic High Level Input Voltage Range High Level Output Voltage Low Level Output Voltage Clock Frequency -25 MHz Version -33 MHz Version (1) Min +4.75 GND - 0.3 +2.0 2.4 Typ Max +5.25 0.8 VCC + 0.3 Unit V V V V 0.5 25 33 -55 TJmax +125 V MHz MHz C C Maximum Operating Junction Temperature 1. This device is not tested at TC = +125C. Testing is performed by setting the junction temperature TJ = +125C and allowing the case and ambient temperatures to rise and fall as necessary so as not to exceed the maximum junction temperature. 9 2116A-HIREL-09/02 Thermal Considerations General Thermal Considerations This section is only given as user information. As microprocessors are becoming more complex and requiring more power, the need to efficiently cool the device becomes increasingly more important. In the past, the TS68000 Family, has been able to provide a 0-70C ambient temperature part for speeds less than 40 MHz. However, the TS68040, which has a 50 MHz arithmetic logic unit (ALU) speed, is specified with a maximum power dissipation for a particular mode, a maximum junction temperature, and a thermal resistance from the die junction to the case. This provides a more accurate method of evaluating the environment, taking into consideration both the air-flow and ambient temperature available. This also allows a user the information to design a cooling method which meets both thermal performance requirements and constraints of the board environment. This section discusses the device characteristics for thermal management, several methods of thermal management, and an example of one method of cooling the TS68040. Thermal Device Characteristics The TS68040 presents some inherent characteristics which should be considered when evaluating a method of cooling the device. The following paragraphs discuss these die/package and power considerations. The TS68040 is being placed in a cavity-down alumina-ceramic 179-pin PGA that has a specified thermal resistance from junction to case of 1C/W. This package differs from previous TS68000 Family PGA packages which were cavity up. This cavity-down design allows the die to be attached to the top surface of the package, which increases the ability of the part to dissipate heat through the package surface or an attached heat sink. The maximum perimeter that the TS68040 allows for a heat sink on its surface without interfering with the capacitor pads is 1.48" x 1.48". The specific dimensions and design of the particular heat sink will need to be determined by the system designer considering both thermal performance requirements and size requirements. The TS68040 has a maximum power rating, which varies depending on the operating frequency and the output buffer mode combination being used. The large buffer output mode dissipates more power than the small, and the higher frequencies of operation dissipate more power than the lower frequencies. The following paragraphs discuss trade-offs in using the different output buffer modes, calculation of specific maximum power dissipation for different modes, and the relationship of thermal resistances and temperatures. Die and Package Power Considerations 10 TS68040 2116A-HIREL-09/02 TS68040 Output Buffer Mode The 68040 is capable of resetting to enable for a combination of either large buffers or small buffers on the outputs of the miscellaneous control signals, data bus, and address bus/transfer attribute pins. The large buffers offer quicker output times, which allow for an easier logic design. However, they do so by driving about 11 times as much current as the small buffers (refer to TS68040 Electrical specifications for current output). The designer should consider whether the quicker timings present enough advantage to justify the additional consideration to the individual signal terminations, the die power consumption, and the required cooling for the device. Since the TS68040 can be powered-up in one of eight output buffer modes upon reset, the actual maximum power consumption for TS68040 rated at a particular maximum operating frequency is dependent upon the power up mode. Therefore, the TS68040 is rated at a maximum power dissipation for either the large buffers or small buffers at a particular frequency (refer to TS68040 Electrical specifications). This allows the possibility of some of the thermal management to be controlled upon reset. The following equation provides a rough method to calculate the maximum power consumption for a chosen output buffer mode: PD = PDSB + (PDLB - PDSB) * (PINSLB/PINSCLB) where: PD PDSB PDLB PINSLB = Max. power dissipation for output buffer mode selected = Max. power dissipation for small buffer mode (all outputs) = Max. power dissipation for large buffer mode (all outputs) = Number of pins large buffer mode (1) PINSCLB = Number of pins capable of the large buffer mode Table 6 shows the simplified relationship on the maximum power dissipation for eight possible configurations of output buffer modes. Table 6. Maximum Power Dissipation for Output Buffer Mode Configurations Output Configuration Data Bus Small Buffer Small Buffer Small Buffer Small Buffer Large Buffer Large Buffer Large Buffer Large Buffer Address Bus and Transfer Attrib. Small Buffer Small Buffer Large Buffer Large Buffer Small Buffer Small Buffer Large Buffer Large Buffer Misc. Control Signals Small Buffer Large Buffer Small Buffer Large Buffer Small Buffer Large Buffer Small Buffer Large Buffer Maximum Power Dissipation PD PDSB PDSB + (PDLB - PDSB) * 13% PDSB + (PDLB - PDSB) * 52% PDSB + (PDLB - PDSB) * 65% PDSB + (PDLB - PDSB) * 35% PDSB + (PDLB - PDSB) * 48% PDSB + (PDLB - PDSB) * 87% PDSB + (PDLB - PDSB) * 100% 11 2116A-HIREL-09/02 To calculate the specific power dissipation of a specific design, the termination method of each signal must be considered. For example, a signal output that is not connected would not dissipate any additional power if it were configured in the large buffer rather than the small buffer mode. Relationships Between Thermal Resistances and Temperatures Since the maximum operating junction temperature has been specified to be 125C. The maximum case temperature, TC, in C can be obtained from: TC = TJ - PD * JC where: TC TJ PD JC = Maximum case temperature = Maximum junction temperature = Maximum power dissipation of the device = Thermal resistance between the junction of the die and the case (2) In general, the ambient temperature, TA, in C is a function of the following formula: TA = TJ - PD * JC - PD * CA (3) Where the thermal resistance from case to ambient, CA, is the only user-dependent parameter once a buffer output configuration has been determined. As seen from equation (3), reducing the case to ambient thermal resistance increases the maximum operating ambient temperature. Therefore, by utilizing such methods as heat sinks and ambient air cooling to minimize the CA, a higher ambient operating temperature and/or a lower junction temperature can be achieved. However, an easier approach to thermal evaluation uses the following formulas: TA = TJ - PD * JA or alternatively, TJ = TA - PD * JA where: JA = thermal resistance from the junction to the ambient (JC + CA). This total thermal resistance of a package, JA, is a combination of its two components, JC and CA. These components represent the barrier to heat flow from the semiconductor junction to the package (case) surface (JC) and from the case to the outside ambient (JC). Although JC is device related and cannot be influenced by the user, CA is user dependent. Thus, good thermal management by the user can significantly reduce CA achieving either a lower semiconductor junction temperature or a higher ambient operating temperature. Thermal Management Techniques To attain a reasonable maximum ambient operating temperature, a user must reduce the barrier to heat flow from the semiconductor junction to the outside ambient (JA). The only way to accomplish this is to significantly reduce CA by applying such thermal management techniques as heat sinks and ambient air cooling. The following paragraphs discuss some results of a thermal study of the TS68040 device without using any thermal management techniques; using only air-flow cooling, using only a heat sink, and using heat sink combined with air-flow cooling. (5) (4) 12 TS68040 2116A-HIREL-09/02 TS68040 Thermal Characteristics in Still Air A sample size of three TS68040 packages was tested in free-air cooling with no heat sink. Measurements showed that the average JA was 22.8C/W with a standard deviation of 0.44C/W. The test was performed with 3W of power being dissipated from within the package. The test determined that JA will decrease slightly for the increasing power dissipation range possible. Therefore, since the variance in JA within the possible power dissipation range is negligible, it can be assumed for calculation purposes that JA is valid at all power levels. Using the formulas introduced previously, Table 7 shows the results of a maximum power dissipation of 3 and 5W with no heat sink or air-flow (refer to Table 6 to calculate other power dissipation values). Table 7. Thermal Parameters With No Heat Sink or Air-flow Defined Parameters PD 3 Watts 5 Watts TJ 125C 125C JC 1C/W 1C/W Measured JA 21.8C/W 21.8C/W CA = JA - JC 20.8C/W 20.8C/W Calculated TC = TJ - PD * JC 122C 120C TA = TJ - PD * JA 59.6C 16C As seen by looking at the ambient temperature results, most users will want to implement some type of thermal management to obtain a more reasonable maximum ambient temperature. Thermal Characteristics in Forced Air A sample size of three TS68040 packages was tested in forced air cooling in a wind tunnel with no heat sink. This test was performed with 3W of power being dissipated from within the package. As previously mentioned, since the variance in JA within the possible power range is negligible, it can be assumed for calculation purposes that JA is constant at all power levels. Using the previous formulas, Table 8 shows the results of the maximum power dissipation at 3 and 5W with air-flow and no heat sink (refer to Table 6 to calculate other power dissipation values). Table 8. Thermal Parameters With Forced Air Flow and No Heat Sink Thermal Mgmt. Technique Air-flow velocity 100 LFM 250 LFM 500 LFM 750 LFM 1000 LFM 100 LFM 250 LFM 500 LFM 750 LFM 1000 LFM PD 3W 3W 3W 3W 3W 5W 5W 5W 5W 5W Defined Parameters TJ 125C 125C 125C 125C 125C 125C 125C 125C 125C 125C JC 1C/W 1C/W 1C/W 1C/W 1C/W 1C/W 1C/W 1C/W 1C/W 1C/W Measured JA 11.7C/W 10C/W 8.9C/W 8.5C/W 8.3C/W 11.7C/W 10C/W 8.9C/W 8.5C/W 8.3C/W CA 10.7C/W 9C/W 7.9C/W 7.5C/W 7.3C/W 10.7C/W 9C/W, 7.9C/W 7.5C/W 7.3C/W Calculated TC 122C 122C 122C 122C 122C 120C 120C 120C 120C 120C TA 89.9C 95C 98.3C 99.5C 100.1C 66.5C 75C 80.5C 82.5C 83.5C 13 2116A-HIREL-09/02 By reviewing the maximum ambient operating temperatures, it can be seen that by using the all-small-buffer configuration of the TS68040 with a relatively small amount of air flow (100 LFM), a 0-70C ambient operating temperature can be achieved. However, depending on the output buffer configuration and available forced-air cooling, additional thermal management techniques may be required. Thermal Characteristics with a Heat Sink In choosing a heat sink the designer must consider many factors: heat sink size and composition, method of attachment, and choice of a wet or dry connection. The following paragraphs discuss the relationship of these decisions to the thermal performance of the design noticed during experimentation. The heat sink size is one of the most significant parameters to consider in the selection of a heat sink. Obviously a larger heat sink will provide better cooling. However, it is less obvious that the most benefit of the larger heat sink of the pin fin type used in the experimentation would be at still air conditions. Under forced-air conditions as low as 100 LFM, the difference between the CA becomes very small (0.4C/W or less). This difference continues to decrease as the forced air flow increases. The particular heat sink used in our testing fit the perimeter package surface area available within the capacitor pads on the TS68040 (1.48" x 1.48") and showed a nice compromise between height and thermal performance needs. The heat sink base perimeter area was 1.24" x 1.30" and its height was 0.49". It was a pin-fin-type (i.e. bed of nails) design composed of Al alloy. The heat sink is shown in Figure 5 can be obtained through Thermalloy Inc. by referencing part number 2338B. Figure 5. Heat Sink Example 14 TS68040 2116A-HIREL-09/02 TS68040 All pin fin heat sinks tested were made from extrusion Al products. The planar face of the heat sink mating to the package should have a good degree of planarity; if it has any curvature, the curvature should be convex at the central region of the heat sink surface to provide intimate physical contact to the PGA surface. All heat sinks tested met this criteria. Nonplanar, concave curvature the central regions of the heat sink will result in poor thermal contact to the package. A specification needs to be determined for the planarity of the surface as part of any heat sink design. Although there are several ways to attach a heat sink to the package, it was easiest to use a demountable heat sink attach called "E-Z attach for PGA packages" developed by Thermalloy (see Figure 6). The heat sink is clamped to the package with the help of a steel spring to a plastic frame (or plastic shoes Besides the height of the heat sink and plastic frame, no additional height added to the package. The interface between the ceramic package and the heat sink was evaluated for both dry and wet (i.e., thermal grease) interfaces in still air. The thermal grease reduced the CA quite significantly (about 2.5 C/W) in still air. Therefore, it was used in all other testing done with the heat sink. According to other testing, attachment with thermal grease provided about the same thermal performance as if a thermal epoxy were used. Figure 6. Heat Sink with Attachment A sample size of one TS68040 package was tested in still air with the heat sink and attachment method previously described. This test was performed with 3W of power being dissipated from within the package. Since the variance in JA within the possible power range is negligible, it can be assumed for calculation purposes that JA is constant at all power levels. Table 9 shows the result assuming a maximum power dissipation of the part at 3 and 5W (refer to Table 6 to calculate other power dissipation values). 15 2116A-HIREL-09/02 Table 9. Thermal Parameters With Heat Sink and No Air Flow Thermal Mgmt. Technique Heat Sink 2338B 2338B PD 3W 5W Defined Parameters TJ 125C 125C JC 1C/W 1C/W Measured JA 14C/W 14C/W CA 13C/W 13C/W Calculated TC 122C 120C TA 83C 55C Thermal Characteristics with a Heat Sink and Forced Air A sample size of three TS68040 packages was tested in forced-air cooling in a wind tunnel with a heat sink. This test was performed with 3W of power being dissipated from within the package. As mentioned previously, the variance in JA within the possible power range is negligible; it can be assumed for calculation purposes that JA is valid at all power levels. Table 10 shows the results, assuming a maximum power dissipation at 3 and 5W with air flow and heat sink thermal management (refer to Table 6 to calculate other power dissipation values). Table 10. Thermal Parameters with Heat Sink and Air Flow Thermal Mgmt. Technique Air-flow 100 LFM 250 LFM 500 LFM 750 LFM 1000 LFM 100 LFM 250 LFM 500 LFM 750 LFM 1000 LFM Heat sink 2338B 2338B 2338B 2338B 2338B 2338B 2338B 2338B 2338B 2338B PD 3W 3W 3W 3W 3W 5W 5W 5W 5W 5W Defined Parameters TJ 125C 125C 125C 125C 125C 125C 125C 125C 125C 125C JC 1C/W 1C/W 1C/W 1C/W 1C/W 1C/W 1C/W 1C/W 1C/W 1C/W Measured JA 3.1C/W 2.2C/W 1.7C/W 1.5C/W 1.4C/W 3.1C/W 2.2C/W 1.7C/W 1.5C/W 1.4C/W CA 2.1C/W 1.2C/W 0.7C/W 0.5C/W 0.4C/W 2.1C/W 1.2C/W 0.7C/W 0.5C/W 0.4C/W Calculated TC 122C 122C 122C 122C 122C 120C 120C 120C 120C 120C TA 115.7C 118.4C 119.9C 120.5C 120.8C 109.5C 114C 116.5C 117.5C 118C Thermal Testing Summary Testing proved that a heat sink in combination with a relatively small amount of air-flow (100 LFM or less) will easily realize a 0-70C ambient operating temperature for the TS68040 with almost any configuration of the output buffers. A heat sink alone may be capable of providing all necessary cooling, depending on the particular heat sink height/size restraints, the maximum ambient operating temperature required, and the output buffer configuration chosen. Also forced air cooling alone may attain a 0-70C ambient operating temperature. However this factor is highly dependent on the output buffer configuration chosen and the available forced air for cooling. Figure 7 is a summary of the test results of the relationship between JA and air-flow for the TS68040. 16 TS68040 2116A-HIREL-09/02 TS68040 Figure 7. Relationship of JA Air-Flow for PGA Table 11. Characteristics Guaranteed Package PGA 179 Symbol J-A J-C J-A J-C Parameter Thermal Resistance Junction-to-ambient Thermal Resistance Junction-to-case Thermal Resistance Junction-to-ambient Thermal Resistance Junction-to-case Value See Figure 7 1 TBD 1 Unit C/W C/W C/W C/W CQFP 196 Mechanical and Environment Marking The microcircuits shall meet all mechanical environmental requirements of either MILSTD-883 for class B devices or for Atmel standard screening. The document where are defined the marking are identified in the related reference documents. Each microcircuit are legible and permanently marked with the following information as minimum: * * * * * * Atmel Logo Manufacturer's Part Number Class B Identification Date-code Of Inspection Lot ESD Identifier If Available Country Of Manufacturing 17 2116A-HIREL-09/02 Quality Conformance Inspection DESC/MIL-STD-883 Is in accordance with MIL-M-38535 and method 5005 of MIL-STD-883. Group A and B inspections are performed on each production lot. Groups C and D inspection are performed on a periodical basis. Electrical Characteristics General Requirements All static and dynamic electrical characteristics specified for inspection purposes and the relevant measurement conditions are given below: * * Table 12: Static electrical characteristics for the electrical variants. Table 13: Dynamic electrical characteristics for TS68040 (25 MHz, 33 MHz). For static characteristics (Table 12), test methods refer to IEC 748-2 method number, where existing. For dynamic characteristics (Table 13), test methods refer to clause "Static Characteristics" on page 18 of this specification. Indication of "min." or "max." in the column test temperature means minimum or maximum operating temperature as defined in sub-clause Table 5 here above. Static Characteristics Table 12. Electrical Characteristics -55C TC TJmax; 4.75V VCC 5.25V unless otherwise specified(1)(2)(3)(4) Symbol VIH VIL VU Iin Characteristic Input High Voltage Input Low Voltage Undershoot Input Leakage Current at 0.5/2.4V Hi-z (Off-state) Leakage Current at 0.5/2.4V Signal Low Input Current VIL = 0.8V Signal High Input Current VIH = 2.0V Output High Voltage Larger Buffers - IOH = 35 mA Small Buffers - IOH = 5 mA AVEC, BCLK BG, CDIS, IPLn, MDIS, PCLK, RSTI, SCn, TBI, TCI, TCK, TEA An, BB, CIOUT, Dn, LOCK, LOCKE, R/W, SIZn, TA, TDO, TIP, TLNn, TMn, TS, TTn, UPAn TMS, TDI, TRST TMS, TDI, TRST -20 Min 2 GND Max VCC 0.8 - 0.8 20 Unit V V V A ITSI -20 20 A IIL IIH VOH -1.1 -0.94 -0.18 -0.16 mA mA 2.4 V 18 TS68040 2116A-HIREL-09/02 TS68040 Table 12. Electrical Characteristics (Continued) -55C TC TJmax; 4.75V VCC 5.25V unless otherwise specified(1)(2)(3)(4) Symbol VOL Characteristic Output Low Voltage Larger buffers - IOL = 35 mA Small buffers - IOL = 5 mA Power Dissipation (TJ = 125C) Larger Buffers Enabled Small Buffers Enabled Min Max 0.5 Unit V PD 7.7 6.3 W Cin Notes: 1. 2. 3. 4. Capacitance - Note 4 25 pF Vin = 0V, f = 1 MHz All testing to be performed using worst-case test conditions unless otherwise specified. Maximum operating junction temperature (TJ) = +125. Minimum case operating temperature (TC) = -55. This device is not tested at TC = +125. Testing is performed by setting the junction temperature TJ = +125and allowing the case and ambient temperatures to rise and fall as necessary so as not to exceed the maximum junction temperature. Capacitance is periodically sampled rather than 100% tested. Power dissipation may vary in between limits depending on the application. Dynamic Characteristics Table 13. Clock AC Timing Specifications (see Figure 8) -55C TC TJmax; 4.75V VCC 5.25V unless otherwise specified(1)(2)(3)(4) 25 MHz Num Frequency of Operation 1 2 3 4 4a 4b 5 6, 7 8 8a 8b 9 PCLK Cycle Time PCLK Rise Time PCLK Fall Time (4) 33 MHz Min 20 15 Max 33 25 1.7 1.6 46.67 7 7 30 53.33 8 8 60 3 40 12 12 60 18 18 1000 Unit MHz ns ns ns % ns ns ns ns % ns ns ppm Characteristic Min 20 20 Max 25 25 1.7 1.6 (4) (4) (3)(4) PCLK Duty Cycle Measured at 1.5V 47.5 9.5 9.5 40 52.5 10.5 10.5 50 4 PCLK Pulse Width High Measured at 1.5V PCLK Pulse Width Low Measured at 1.5V BCLK Cycle Time BCLK Rise and Fall Time BCLK Duty Cycle Measured at 1.5V(4) (3)(4) 40 16 16 60 24 24 1000 BCLK Pulse Width High Measured at 1.5V(4) BCLK Pulse Width Low Measured at 1.5V PCLK, BCLK Frequency Stability (4) (4) 10 PCLK to BCLK Skew 9 n/a ns Notes: 1. All testing to be performed using worst-case test conditions unless otherwise specified. 2. Maximum operating junction temperature (TJ) = +125. Minimum case operating temperature (TC) = -55. This device is not tested at TC = +125. Testing is performed by setting the junction temperature TJ = +125and allowing the case and ambient temperatures to rise and fall as necessary so as not to exceed the maximum junction temperature. 3. Specification value at maximum frequency of operation. 4. If not tested, shall be guaranteed to the limits specified. 19 2116A-HIREL-09/02 Figure 8. Clock Input Timing Table 14. Output AC Timing Specifications(1) (Figure 9 to Figure 15) These output specifications are only for 25 MHz. They must be scaled for lower operating frequencies. Refer to TS6804DH/AD for further information. -55C TC TJmax; 4.75V VCC 5.25V unless otherwise specified.(2)(3)(4) 25 MHz Large Buffer(1) Num 11 12 13 14 18 19 20 21 26 27 28 29 30 38 Characteristic BCLK to address CIOUT, LOCK, LOCKE, R/W, SIZn, TLN, TMn, UPAn valid(5) BCLK to output invalid (output hold) BCLK to TS valid BCLK to TIP valid BCLK to data-out valid (6) (6) 33 MHz Small Buffer(1) Large Buffer(1) Min 6.50 6.50 30 30 32 6.50 6.50 6.50 6.50 6.50 20 40 6.50 14 14 18 6.50 14 42 18 14 6.50 15 20 28 15 17 26 18 18 20 Max 18 Small Buffer(1) Min 6.50 6.50 6.50 6.50 6.50 6.50 6.50 6.50 14 14 6.50 14 14 6.50 15 20 35 15 17 33 25 25 27 Max 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min 9 9 9 9 9 9 9 9 (5) (5) Max 21 Min 9 9 Max 30 21 21 23 9 9 9 9 9 BCLK to data-out invalid (output hold) BCLK to output low impedance (5)(6) BCLK to data-out high impedance BCLK to multiplexed address valid 20 31 9 19 19 19 19 9 19 19 9 BCLK to multiplexed address driven BCLK to multiplexed address high impedance(5)(6) BCLK to multiplexed data driven(6) BCLK to multiplexed data valid(6) 18 9 19 33 18 19 9 BCLK to address CIOUT, LOCK, LOCKE, R/W, SIZn, TS, TLNn, TMn, TTn, UPAn high impedance(5) BCLK to BB, TA, TIP high impedance BCLK to BR, BB valid BCLK to MI valid BCLK to TA valid BCLK to IPEND, PSTn, RSTO valid 39 40 43 48 50 19 9 9 9 9 28 21 21 21 21 19 9 9 9 9 28 30 30 30 30 14 6.50 6.50 6.50 6.50 23 18 18 18 18 14 6.50 6.50 6.50 6.50 23 25 25 25 25 ns ns ns ns ns 20 TS68040 2116A-HIREL-09/02 TS68040 Notes: 1. Output timing is specified for a valid signal measured at the pin. Large buffer timing is specified driving a 50 transmission line with a length characterized by a 2.5 ns one-way propagation delay, terminated through 50 to 2.5V. Large buffer output impedance is typically 3, resulting in incident wave switching for this environment. Small buffer timing is specified driving an unterminated 30 transmission line with a length characterized by a 2.5 ns one-way propagation delay. Small buffer output impedance is typically 30; the small buffer specifications include approximately 5 ns for the signal to propagate the length of the transmission line and back. 2. All testing to be performed using worst-case test conditions unless otherwise specified. 3. The following pins are active low: AVEC, BG, BS, BR, CDIS, CIOUT, IPEND, IPLO, IPL1, IPL2, LOCK, LOCKE, MDIS, MI, RST0, RSTI, TA, TBI, TCI, TEA, TIP, TRST, TS and W of R/W. 4. Maximum operating junction temperature (TJ) = +125. Minimum case operating temperature (TC) = -55. This device is not tested at TC = +125. Testing is performed by setting the junction temperature TJ = +125and allowing the case and ambient temperatures to rise and fall as necessary so as not to exceed the maximum junction temperature. 5. Timing specifications 11, 20 and 38 for address bus output timing apply when normal bus operation is selected. Specifications 26, 27 and 28 should be used when the multiplexed bus mode of operation is enabled. 6. Timing specifications 18 and 19 for data bus output timing apply when normal bus operation is selected. Specifications 28 and 29 should be used when the multiplexed bus mode of operation is enabled. Table 15. Input AC Timing Specifications (Figure 9 to Figure 15) -55C TC TJmax; 4.75V VCC 5.25V unless otherwise specified(1)(2)(3)(4) 25 MHz Num 15 16 17 22a 22b 22c 22d 23 24 25 31 32 33 34 35 36 37 41a 41b 41c 41d 42 44a 44b Characteristic Data-in Valid to BCLK (Setup) BCLK to Data-in Invalid (Hold) BCLK to Data-in High Impedance (Read Followed By Write) TA Valid to BCLK (Setup) TEA Valid to BCLK (Setup) TCI Valid to BCLK (Setup) TBI Valid to BCLK (Setup) BCLK to TA, TEA, TCI, TBI Invalid (Hold) AVEC Valid to BCLK (Setup) BCLK to AVEC Invalid (Hold) DLE Width High Data-in Valid to DLE (Setup) DLE to Data-in Invalid (Hold) BCLK to DLE Hold DLE High to BCLK Data-in Valid to BCLK (DLE Mode Setup) BCLK Data-in Invalid (DLE Mode Hold) BB Valid to BCLK (Setup) BG Valid to BCLK (Setup) CDIS, MDIS Valid to BCLK (Setup) IPLn Valid to BCLK (Setup) BCLK to BB, BG, CDIS, IPLn, MDIS Invalid (Hold) Address Valid to BCLK (Setup) SIZn Valid BCLK (Setup) 10 10 10 11 2 5 2 8 2 8 3 16 5 4 7 8 10 4 2 8 12 Min. 5 4 49 10 10 10 10 2 5 2 8 2 8 3 12 5 4 7 7 8 3 2 7 8 Max. 33 MHz Min. 4 4 36.5 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 21 2116A-HIREL-09/02 Table 15. Input AC Timing Specifications (Figure 9 to Figure 15) (Continued) -55C TC TJmax; 4.75V VCC 5.25V unless otherwise specified(1)(2)(3)(4) 25 MHz Num 44c 44d 44e 45 46 47 49 51 52 53 54 Notes: Characteristic TTn Valid to BCLK (Setup) R/W Valid to BCLK (Setup) SCn Valid to BCLK (Setup) BCLK to Address SIZn, TTn, R/W, SCn Invalid (Hold) TS Valid to BCLK (Setup) BCLK to TS Invalid (Hold) BCLK to BB High Impedance (68040 Assumes Bus Mastership) RSTI Valid to BCLK BCLK to RSTI Invalid Mode Select Setup to RSTI Negated (4) 33 MHz Min. 8.5 5 11 2 9 2 9 9 4 2 20 Max. Unit ns ns ns ns ns ns ns ns ns ns Min. 6 6 10 2 5 2 Max. 5 2 20 RSTI Negated to Mode Selects Invalid(4) 2 2 ns 1. All testing to be performed using worst-case test conditions unless otherwise specified. 2. The following pins are active low: AVEC, BG, BS, BR, CDIS, CIOUT, IPEND, IPLO, IPL1, IPL2, LOCK, LOCKE, MDIS, MI, RST0, RSTI, TA, TBI, TCI, TEA, TIP, TRST, TS and W of R/W. 3. Maximum operating junction temperature (TJ) = +125. Minimum case operating temperature (TC) = -55. This device is not tested at TC = +125. Testing is performed by setting the junction temperature TJ = +125and allowing the case and ambient temperatures to rise and fall as necessary so as not to exceed the maximum junction temperature. 4. The levels on CDIS, MDIS, and the IPL2-IPL0 signals enable or disable the multiplexed bus mode, data latch enable mode, and driver impedance selection respectively. 22 TS68040 2116A-HIREL-09/02 TS68040 Figure 9. Read/Write Timing Note: Transfer attribute signals UPAN, SIZN, TTN, TMN, TLNN, R/W, LOCK, LOCKE, CIOUT Table 16. JTAG Timing Application (Figure 16 to Figure 19) -55C TC TJmax; 4.75V VCC 5.25V unless otherwise specified(1)(2) Num Characteristic TCK Frequency 1 2 3 4 5 6 7 8 9 10 11 12 13 TCK Cycle Time TCK Clock Pulse Width Measured at 1.5V TCK Rise and Fall Times TRST Setup Time to TCK Falling Edge TRST Assert Time Boundary Scan Input Data Setup Time Boundary Scan Input Data Hold Time TCK to Output Data Valid TCK to Output High Impedance TMS, TDI Data Setup Time TMS, TDI Data Hold Time TCK to TDO Data Valid TCK to TDO High Impedance Min 0 100 40 0 40 100 50 50 0 0 20 5 0 0 20 20 50 50 10 Max 10 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns 23 2116A-HIREL-09/02 Notes: 1. All testing to be performed using worst-case test conditions unless otherwise specified. 2. Maximum operating junction temperature (TJ) = +125. Minimum case operating temperature (TC) = -55. This device is not tested at TC = +125. Testing is performed by setting the junction temperature TJ = +125 and allowing the case and ambient temperatures to rise and fall as necessary so as not to exceed the maximum junction temperature. Table 17. Boundary Scan Instruction Codes Bit 2 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 Instruction Selected Extest Highz Sample/Preload DRVCTLT Shutdown Private DRVCTLS Bypass Test Data Register Accessed Boundary Scan Bypass Boundary Scan Boundary Scan Bypass Bypass Boundary Scan Bypass Switching Test Circuit and Waveforms Figure 10. Address and Data Bus Timing -- Multiplexed Bus Mode 24 TS68040 2116A-HIREL-09/02 TS68040 Figure 11. DLE Timing Burst Access Figure 12. Bus Arbitration Timing 25 2116A-HIREL-09/02 Figure 13. Snoop Hit Timing 26 TS68040 2116A-HIREL-09/02 TS68040 Figure 14. Snoop Miss Timing Figure 15. Other Signal Timing 27 2116A-HIREL-09/02 Figure 16. Clock Input Timing Diagram Figure 17. TRST Timing Diagram Figure 18. Boundary Scan Timing Diagram 28 TS68040 2116A-HIREL-09/02 TS68040 Figure 19. Test Access Port Timing Diagram Functional Description Programming Model The TS68040 integrates the functions of the integer unit, MMU, and FPU. As shown in Figure 20, the registers depicted in the programming model provide access and control for the three units. The registers are partitioned into two levels of privilege: user and supervisor. User programs, executing in the user mode, can only use the resources of the user model. System software, executing in the supervisor mode, has unrestricted access to all processor resources. The integer portion of the user programming model, consisting of 16, general-purpose, 32-bit registers and two control registers, is the same as the user programming model of the TS68030. The TS68040 user programming model also incorporates the TS68882 programming model consisting of eight, floating-point, 80-bit data registers, a floatingpoint control register, a floating-point status register, and a floating-point instruction address register. The supervisor programming model is used exclusively by TS68040 system programmers to implement operating system functions, I/O control, and memory management subsystems. This supervisor/user distinction in the TS68000 architecture was carefully planned so that all application software can be written to execute in the nonprivileged user mode and migrate to the TS68040 from any TS68000 platform without modification. Since system software is usually modified by system designers when porting to a new design, the control features are properly placed in the supervisor programming model. For example, the transparent translation registers of the TS68040 can only be read or written by the supervisor software; the programming resources of user application programs are unaffected by the existence of the transparent translation registers Registers D0-D7 are data registers containing operands for bit and bit field (1- to 32-bit), byte (8-bit), word (16-bit), long-word (32-bit), and quad-word (64-bit) operations. Registers A0-A6 and the stack pointer registers (user, interrupt, and master) are address registers that may be used as software stack pointers or base address registers. Register A7 is the user stack pointer in user mode, and is either the interrupt or master stack pointer (A7' or A7'') in supervisor mode. In supervisor mode, the active stack pointer (interrupt or master) is selected based on a bit in the status register (SR). The address 29 2116A-HIREL-09/02 registers may be used for word and long-word operations, and all of the 16 general-purpose registers (D0-D7, A0-A7 in Figure 20) may be used as index registers. The eight, 80-bit, floating-point data registers (FP0-FP7) are analogous to the integer data registers (D0-D7) of all TS68000 Family processors. Floating-point data registers always contain extended-precision numbers. All external operands, regardless of the data format, are converted to extended-precision values before being used in any floating-point calculation or stored in a floating-point data register. The program counter (PC) usually contains the address of the instruction being executed by the TS68040. During instruction execution and exception processing, the processor automatically increments the contents of the PC or places a new value in the PC, as appropriate. The status register (SR in the supervisor programming model) contains the condition codes that reflect the results of a previous operation and can be used for conditional instruction execution in a program. The lower byte of the SR is accessible in user mode as the condition code register (CCR). Access to the upper byte of the SR is restricted to the supervisor mode. As part of exception processing, the vector number of the exception provides an index into the exception vector table. The base address of the exception vector table is stored in the vector base register (VBR). The displacement of an exception vector is added to the value in the VBR when the TS68040 accesses the vector table during exception processing. Alternate function code registers, SFC and DFC (source and destination), contain 3-bit function codes. Function codes can be considered extensions of the 32-bit linear address. Function codes are automatically generated by the processor to select address spaces for data and program accesses at the user and supervisor modes. The alternate function code registers are used by certain instructions to explicitly specify the function codes for various operations. The cache control register (CACR) controls enabling of the on-chip instruction and data caches of the TS68040. The supervisor root pointer (SRP) and user root pointer (URP) registers point to the root of the address translation table tree to be used for supervisor mode and user mode accesses. The URP is used if FC2 of the logical address is zero, and the SRP is used if FC2 is one. The translation control register (TC) enables logical-to-physical address translation and selects either 4K or 8K page sizes. As shown in Figure 20, there are four transparent translation registers - ITT0 and ITT1 for instruction accesses and DTT0 and DTT1 for data accesses. These registers allow portions of the logical address space to be transparently mapped and accessed without the use of resident descriptors in an ATC. The MMU status register (MMUSR) contains status information from the execution of a PTEST instruction. The PTEST instruction searches the translation tables for the logical address as specified by this instruction's effective address field and the DFC. The 32-bit floating-point control register (FPCR) contains an exception enable byte that enables disables traps for each class of floating-point exceptions and a mode byte that sets the user-selectable modes. The FPCR can be read or written to by the user and is cleared by a hardware reset or a restore operation of the null state. When cleared, the FPCR provides the IEEE 754 standard defaults. The floating-point status register (FPSR) contains a condition code byte, quotient bits, an exception status byte, and an accrued exception byte. All bits in the FPSR can be read or written by the user. Execution of most floating-point instructions modifies this register. 30 TS68040 2116A-HIREL-09/02 TS68040 For the subset of the FPU instructions that generate exception traps, the 32-bit floatingpoint instruction address register (FPIAR) is loaded with the logical address of an instruction before the instruction is executed. This address can then be used by a floating-point exception handler to locate a floating-point instruction that has caused an exception. The move floating-point data register (FMOVE) instruction (to from the FPCR, FPSR, or FPIAR) and the move multiple data registers (FMOVEN) instruction cannot generate floating-point exceptions; therefore, these instructions do not modify the FPIAR. Thus, the FMOVE and FMOVEM instructions can be used to read the FPIAR in the trap handler without changing the previous value. Figure 20. Programming Model 31 2116A-HIREL-09/02 Data Types and Addressing Modes Table 18. Data Types Operand Data Type Bit Bit Field BCD Byte Integer Word Integer Long-word Integer Quad-word Integer 16-byte Single-precision Real Double-precision Real Extended-precision Real Note: 1. IU = Integer Unit. The TS68040 supports the basic data types shown in Table 18. Some data types apply only to the integer unit, some only to the FPU, and some to both the integer unit and the FPU. In addition, the instruction set supports operations on other data types such as memory addresses. Size 1-bit 1-32 bits 32 bits 8 bits 16 bits 32 bits 64 bits 128 bits 32 bits 64 bits 80 bits Execution Unit (IU(1), FPU) IU IU IU IU, FPU IU, FPU IU, FPU IU IU FPU FPU FPU Any two data registers Memory-only, aligned 16-byte boundary 1-bit sign, 8-bit exponent, 23-bit mantissa 1-bit sign, 11-bit exponent, 52-bit mantissa 1-bit sign, 15-bit exponent, 64-bit mantissa Field of consecutive bits Packaged: 2 digits byte Unpacked: 1 digit byte Notes The three integer data formats that are common to both the integer unit and the FPU (byte, word, and long word) are the standard twos-complement data formats defined in the TS68000 Family architecture. Whenever an integer is used in a floating-point operation, the integer is automatically converted by the FPU to an extended-precision floatingpoint number before being used. The ability to effectively use integers in floating-point operations saves user memory because an integer representation of a number usually requires fewer bits than the equivalent floating-point representation. Single- and double-precision floating-point data formats are implemented in the FPU as defined by the IEEE standard. These data formats are the main floating-point formats and should be used for most calculations involving real numbers. The extended-precision data format is also in conformance with the IEEE standard, but the standard does not specify this format to the bit level as it does for single- and double-precision. The memory format for the FPU consists of 96 bits (three long words). Only 80 bits are actually used; the other 16 bits are reserved for future use and for longword alignment of the floating-point data structures in memory. The extended-precision format has a 15-bit exponent, a 64-bit mantissa, and a 1-bit mantissa sign. Extendedprecision numbers are intended for use as temporary variables, intermediate values, or where extra precision is needed. The TS68040 addressing modes are shown in Table 19. The register indirect addressing modes support post-increment, predecrement, offset, and indexing, which are particularly useful for handling data structures common to sophisticated applications and high-level languages. The program counter indirect mode also has indexing and offset capabilities; this addressing mode is typically required to support positionindependent software. In addition to these addressing modes, the TS68040 provides index sizing and scaling features that enhance software performance. Data formats are supported orthogonally by all arithmetic operations and by all appropriate addressing modes. 32 TS68040 2116A-HIREL-09/02 TS68040 Table 19. Addressing Modes Addressing Modes Register Direct Date Register Direct Address Register Direct Register Indirect Address Register Indirect Address Register Indirect With Postincrement Address Register Indirect With Predecrement Address Register Indirect With Displacement Register Indirect With Index Address Register Indirect With Index (8-bit Displacement) Address Register Indirect With Index (Base Displacement) Memory Indirect Memory Indirect Postincrement Memory Indirect Preindexed Program Counter Indirect With Displacement Program Counter Indirect With Index PC Indirect With Index (8-bit Displacement) PC Indirect With Index (Base Displacement Program Counter Memory Indirect PC Memory Indirect Postindexed PC Memory Indirect Preindexed Absolute Absolute Short Absolute Long Immediate Note: Syntax Dn An (An) (An) (An) (d16, An) (d8, An, Xn) (bd, An, Xn) ([bd, An], Xn, od) ([bd, An, Xn], od) (d16, PC) (d8, PC, Xn) (bd, PC, Xn) ([bd, PC], Xn, od) ([bd, PC, Xn], od) xxx.W xxx.L # (data) DN = AN = d8, d16 = Xn = Data register, D0-D7 Address register, A0-A7 A twos-complement or sign-extended displacement; added as part of the effective address calculation; size is 8 (d8) or 16 (d16) bits; when omitted, assemblers use a value of zero. Address or data register used as an index register; form is Xn, SIZE*SCALE, where SIZE is W or L (indicates index register size) and SCALE is 1, 2, 4 or 8 (index register os multiplied by SCALE); use of SIZE and or SCALE is optional. A twos-complement base displacement; when present, size can be 16 or 32 bits. Outer displacement added as part of effective address calculation after any memory indirection; use is optional with a size of 16 or 32 bits. Program counter. Immediate value of 8, 16 or 32 bits. Effective address. Used as indirect address to long-word address. - Instruction Set Overview bd = od = PC = (data) = () = [] = 33 2116A-HIREL-09/02 The instruction provided by the TS68040 are listed in Table 20. The instruction set has been tailored to support high-level languages and is optimized for those instructions most commonly executed (however, all instructions listed are fully supported). Many instructions operate on bytes, words, and long words, and most instructions can use any of the addressing modes of Table 19. Table 20. Instruction Set Summary Mnemonic ABCD ADD ADDA ADDI ADDQ ADDX AND ANDI ASL, ASR Bcc BCHG BCLR BFCHG BFCLR BFEXTS BFEXTU BFFFO BFINS BFSET BFTST BKPT BRA BSET BSR BTST CAS CAS2 CHK CHK2 CINV(1) CLR CMP CMPA CMPI CMPM CMP2 CPUSH(1) DBCC DIVS, DIVSL DIVU, DIVUL EOR EORI EXG EXT, EXTB Test Condition, Decrement And Branch Signed Divide Unsigned Divide Logical Exclusive OR Logical Exclusive OR Immediate Exchange Registers Sign Extend Description Add Decimal With Extend Add Add Address Add Immediate Add Quick Add With Extend Logical AND Logical AND Immediate Arithmetic Shift Left And Right Branch Conditionally Test Bit And Change Test Bit And Clear Test Bit Field And Change Test Bit Field And Clear Signed Bit Field Extract Unsigned Bit Field Extract Bit Field Find First One Bit Field Insert Test Bit Field And Set Test Bit Field Breakpoint Branch Test Bit And Set Branch To Subroutine Test Bit Compare And Swap Operands Compare And Swap Dual Operands Check Register Against Bounds Check Register Against Upper And Lower Bounds Invalidate Cache Entries Clear Compare Compare Address Compare Immediate Compare Memory To Memory Compare Register Against Upper And Lower Bounds Push Then Invalidate Cache Entries 34 TS68040 2116A-HIREL-09/02 TS68040 Table 20. Instruction Set Summary (Continued) Mnemonic ILLEGAL JMP JSR LEA LINK LSL, LSR MOVE MOVE16(1) MOVEA MOVE CCR MOVE SR MOVE USP MOVEC(1) MOVEM MOVEP MOVEQ MOVES(1) MULS MULU NBCD NEG NEGX NOP NOT OR ORI PACK PEA PFLUSH(1) PTEST(1) RESET ROL, ROR ROXL, ROXR RTD RTE RTR RTS Description Take Illegal Instruction Trap Jump Jump To Subroutine Load Effective Address Link And Allocate Logical Shift Left And Right Move 16-byte Block Move Move Address Move Condition Code Register Move Status Register Move User Stack Pointer Move Control Register Move Peripheral Move Quick Move Alternate Address Space Move Multiply Signed Multiply Unsigned Multiply Negate decimal with extend Negate Negate with extend No operation Logical complement Logical Inclusive OR Logical Inclusive OR Immediate Pack BCD Push Effective Address Flush Entry(ies) In The ATCs Test A Logical Address Reset External Devices Rotate Left And Right Rotate With Extend Left And Right Return And Deallocate Return From Exception Return And Restore Codes Return From Subroutine 35 2116A-HIREL-09/02 Table 20. Instruction Set Summary (Continued) Mnemonic SBCD Scc STOP SUB SUBA SUBI SUBQ SUBX SWAP TAS TRAP TRAPcc TRAPV TST Description Substract Decimal With Extend Set Conditionally Stop Subtract Subtract Address Subtract Immediate Subtract Quick Subtract With Extend Swap Register Words Test Operand And Set Trap Trap Conditionally Trap On Overflow Trap Operand UNLK Unlink UNPK Unpack BCD Note: 1. TS6840 additions or alterations to the TS68030 and TS68881/TS68882 instructions sets. Table 21. Floating-point instructions Mnemonic FABS(1) FADD(1) FBcc FCMP FDBcc FDIV(1) FMOVE(1) FMOVEM FMUL(1) FNEG(1) FRESTORE FSAVE FScc FSQRT(1) FSUB(1) FTRAPcc FTST Note: Description Floating-point Absolute Value Floating-point Add Branch On Floating-point Condition Floating-point Compare Floating-point Decrement And Branch Floating-point Divide Move Floating-point Register Move Multiple Floating-point Registers Floating-point Multiply Floating-point Negate Restore Floating-point Internal State Save Floating-point Internal State Set According To Floating-point Condition Floating-point Square Root Floating-point Substract Trap On Floating-point Condition Floating-point Test 1. TS6840 additions or alterations to the TS68030 and TS68881/TS68882 instructions sets. The TS68040 floating-point instructions, a commonly used subset of the TS68882 instruction set, are implemented in hardware. The remaining unimplemented instructions are less frequently used and are efficiently emulated in software, maintaining compatibility with the TS68881/TS68882 floating-point coprocessors. The TS68040 instruction set includes MOVE16, a new user instruction that allows highspeed transfers of 16-byte blocks between external devices such as memory to memory or coprocessor to memory. 36 TS68040 2116A-HIREL-09/02 TS68040 Instruction and Data Caches Studies have shown that typical programs spend much of their execution time in a few main routines or tight loops. Earlier members of the TS68000 Family took advantage of this locality of reference phenomenon to varying degrees. The TS68040 takes further advantage of cache technology with its two, independent, on-chip, physical address space caches, one for instructions and one for data. The caches reduce the processor's external bus activity and increase CPU throughput by lowering the effective memory access time. For a typical system design, the large caches of the TS68040 yield a very high hit rate, providing a substantial increase in system performance. Additionally, the caches are automatically burstfilled from the external bus whenever a cache miss occurs. The autonomous nature of the caches allows instruction-stream fetches, data-stream fetches, and a third external access to occur simultaneously with instruction execution. For example, if the TS68040 requires both an instruction-stream access and an external peripheral access and if the instruction is resident in the on-chip cache, the peripheral access proceeds unimpeded rather than being queued behind the instruction fetch. If a data operand is also required and if it is resident in the data cache, it can also be accessed without hindering either the instruction access from its cache or the peripheral access external to the chip. The parallelism inherent in the TS68040 also allows multiple instructions that do not require any external accesses to execute concurrently while the processor is performing an external access for a previous instruction. Cache Organization The instruction and data caches are four-way set-associative with 64 sets of four, 16byte lines for a total cache storage of 4K bytes each. As shown in Figure 21, each 16byte line contains an address tag and state information. State information for each entry consists of a valid flag for the entire line in both instruction and data caches and write status for each long word in the data cache. The write status in the data cache signifies whether or not the long-word data is dirty (meaning that the data in the cache has been modified but has not been written back to external memory) for data in copyback pages. 37 2116A-HIREL-09/02 Figure 21. Cache Organization Overview The caches are accessed by physical addresses from the on-chip MMUs. The translation of the upper bits of the logical address occurs concurrently with the accesses into the set array in the cache by the lower address bits. The output of the ATC is compared with the tag field in the cache to determine if one of the lines in the selected set matches the translated physical address. If the tag matches and the entry is valid, then the cache has a hit. If the cache hits and the access is a read, the appropriate long word from the cache line is multiplexed onto the appropriate internal bus. If the cache hits and the access is a write, the data, regardless of size, is written to the appropriate portion of the corresponding longword entry in the cache. When a data cache miss occurs and a previously valid cache line is needed to cache the new line, any dirty data in the old line will be internally buffered and copied back to memory after the new cache line has been loaded. Pushing of dirty data can be forced by the CPUSH instruction. 38 TS68040 2116A-HIREL-09/02 TS68040 Cachability of data in each memory page is controlled by two bits in the page descriptor for each page. Cachable pages may be either write through or copyback, with no writeallocate for misses to write through pages. Non-cachable pages may also be specified as non-cachable I/O, forcing accesses to these pages to occur in order of instruction execution. Cache Coherency The TS68040 has the ability to snoop the external bus during accesses by other bus masters to maintain coherency between the TS68040's caches and external memory systems. External write cycles are snooped by both the instruction cache and data cache; whereas, external read cycles are snooped only by the data cache. In addition, external cycles can be flagged on the bus as snoopable or non snoopable. When an external cycle is marked as snoopable, the bus snooper checks the caches for a coherency conflict based on the state of the corresponding cache line and the type of external cycle. Although the internal execution units and the bus snooper circuit all have access to the on-chip caches, the snooper has priority over the execution units to allow the snooper to resolve coherency discrepancies immediately. Cache Instructions The TS68040 supports the following instructions for cache maintenance. Both instructions may selectively operate on the data or instruction cache. CINV: Invalidates a single line, all lines in a physical page, or the entire cache. CPUSH: Pushes selected dirty data cache lines to memory, then invalidates all selected lines. Operand Transfer Mechanisms Transfer Types The TS68040 external synchronous bus supports multiple masters and overlaps arbitration with data transfers. The bus is optimized to perform high-speed transfers to and from an external cache or memory. The data and address buses are each 32 bits wide. The TS68040 provides two signals (TT1-TT0) that define four types of bus transfers: normal access, MOVE16 access, alternate access, and interrupt acknowledge access. Normal accesses identify normal memory references: MOVE16 accesses are memory accesses by a MOVE16 instruction; and alternate accesses identify accesses to the undefined address spaces (function code values of 0, 3, 4, 7). The interrupt acknowledge access is used to fetch an interrupt vector during interrupt exception processing. During burst read write to cache transfers, the values on the address and transfer type signals do not change; they are the address of the first requested item of the cache line. When the TS68040 request a burst read transfer of a cache line, the address bus indicates the address of the long word in the line needed first, but the memory system is expected to provide data in the following order (modulo 4): 0, 1, 2, 3 (long-word offsets). The first address needed may not be from offset 0; nevertheless, all four long words must be transferred. Burst writes occur in a similar manner. Bus snooping ensures that data in main memory is consistent with data in the on-chip caches. If an alternate bus master is performing a read transfer on the bus and snooping is enabled, and if the snoop logic determines that the on-chip data cache has dirty data (data valid but not consistent with memory) for this transfer, the memory is prevented from responding to the read request, and the TS68040 supplies the data directly to the master. If the alternate master is performing a write transfer on the bus and snooping is enabled, and if the snooper determines that one of the on-chip caches has a valid line for this request, then the snooper may either invalidate or update the line as selected by the snoop control signals. Burst Transfer Operation Bus Snooping 39 2116A-HIREL-09/02 Exception Processing The TS68040 provides the same extensions to the exception stacking process as the TS68030. If the M bit in the status register is set, the master stack pointer is used for all task-related exceptions. When a nontask-related exception occurs (i.e., an interrupt), the M bit is cleared, and the interrupt stack pointer is used. This feature allows a task's stack area to be carried within a single processor control block, and new tasks may be initiated by simply reloading the master stack pointer and setting the M bit. The externally generated exceptions are interrupts, bus errors, and reset conditions. The interrupts are requests from external devices for processor action; whereas, the bus error and reset signals are used for access control and processor initialization. The internally generated exceptions come from instructions, address errors, tracing, or breakpoints. The TRAP, TRAPcc, TRAPVcc, FTRAPcc, CHK, CHK2, and DIV instructions can all generate exceptions as part of their instruction execution. Tracing behaves like a very high-priority, internally generated interrupt whenever it is processed. The other internally generated exceptions are caused by unimplemented floating-point instructions, illegal instructions, instruction fetches from odd addresses, and privilege violations. Finally, the MMU can generate exceptions, for access violations and for when invalid descriptors are encountered during table searches. Exception processing for the TS68040 occurs on the following sequence: 1. an internal copy is made of the status register, 2. the vector number of the exception is determined, 3. current processor status is saved, 4. the exception vector offset is determined by multiplying the vector number by four. This offset is then added to the contents of the VBR to determine the memory address of the exception vector. The instruction at the address given in the exception vector is fetched, and normal instruction decoding and execution is started. Memory Management Units The full addressing range of the TS68040 is 4G bytes (4,294,967,296 bytes). However, most TS68040 systems implement a much smaller physical memory. Nonetheless, by using virtual memory techniques, the system can be made to appear to have a full 4G bytes of physical memory available to each user program. The independent instruction and data MMUs fully support demand paged virtual-memory operating systems with either 4K or 8K page sizes. In addition to its main function of memory management, each MMU protects supervisor areas from accesses by user programs and also provides write protection on a page-by-page basis. For maximum efficiency, each MMU operates in parallel with other processor activities. Because logical-to-physical address translation is one of the most frequently executed operations of the TS68040 MMUs, this task has been optimized. Each MMU initiates address translation by searching for a descriptor containing the address translation information in the ATC. If the descriptor does not reside in the ATC, then the MMU performs external bus cycles via the bus controller to search the translation tables in physical memory. After being located, the page descriptor is loaded into the ATC, and the address is correctly translated for the access, provided no exception conditions are encountered. Translation Mechanism 40 TS68040 2116A-HIREL-09/02 TS68040 Address Translation Cache An integral part of the translation function previously described is the dual cache memory that stores recently used logical-to-physical address translation information (page descriptors) for instruction and date accesses. These caches are 64-entry, four-way, set associative. Each ATC compare the logical address of the incoming access against its entries. If one of the entries matches, there is a hit, and the ATC sends the physical address to the bus controller, which then starts the external bus cycle (provided there was no hit in the corresponding cache for the access). The translation tables of the TS68040 have a three level tree structure and reside in main memory. Since only a portion of the complete tree needs to exist at any one time, the tree structure minimizes the amount of memory necessary to set up the tables for most programs. As shown in Figure 20, either the user root pointer or the supervisor root pointer points to the first level table, depending on the values of the function code for an access. Table entries at the second level of the tree (pointer tables) contain pointers to the third level (page tables). Entries in the page tables contain either page descriptors or indirect pointers to page descriptors. The mechanism for performing table search operations uses portions of the logical address (as indices) at each level of the search. All addresses in the translation table entries are physical addresses. Figure 22. Translation Table Structure Translation Tables There are two variations of table searches for both 4K and 8K page sizes: normal searches and indirect searches. An indirect search differs in that the entry in the third level page table contains a pointer to a page descriptor rather than the page descriptor itself. Entries in the translation tables contain control and status information on addition to the physical address information. Control bits specify write protection, limit access to supervisor only, and determine cachability of data in each memory page. Each page descriptor also has two user-programmable bits that appear on the UPA0 and UPA1 signals during an external access for use as address modifier bits. 41 2116A-HIREL-09/02 A global bit can be set in each page descriptor to prevent flushing of the ATC entry for that page by some PFLUSH instruction variants, allowing system ATC entries to remain resident during task swaps. If these special PFLUSH instructions are not used, this bit can be user defined. The MMUs automatically maintain access history information for the pages by updating the used (U) and modified (M) status bits. MMU Instructions The MMU instructions supported by the TS68040 are as follows: PFLUSH: Allows flushing of either selected ATC entries by function code and logical address or the entire ATCs. PTEST: Takes an address and function code and searches the translation tables for the corresponding entry, which is then loaded into the ATC. The results of the search are available in the MMU status register and are often useful in determining the cause of a fault. All of the TS68040 MMU instructions are privileged and can only be executed from the supervisor mode. Transparent Translation Four transparent translation registers, two each for instruction and data accesses, have been provided on the TS68040 MMU to allow portions of the logical address space to be transparently mapped and accessed without the need for corresponding entries resident in the ATC. Each register can be used to define a range of logical addresses from 16M bytes to 4G bytes with a base address and a mask. All addresses within these ranges are not mapped, and are optionally protected against user or supervisor accesses and write accesses. Logical addresses in these areas become the physical addresses for memory access. The transparent translation feature allows rapid movement of large blocks of data in memory or I/O space without disturbing the context of the on-chip ATCs or incurring delays associated with translation table searches. Preparation For Delivery Packaging Microcircuits are prepared for delivery in accordance with MIL-M-38510 or Atmel standard. Certificate of Compliance Atmel offers a certificate of compliances with each shipment of parts, affirming the products are in compliance either with MIL-STD-883 or Atmel standard and guarantying the parameters not tested at temperature extremes for the entire temperature range. Handling MOS devices must be handled with certain precautions to avoid damage due to accumulation of static charge. Input protection devices have been designed in the chip to minimize the effect of this static buildup. However, the following handling practices are recommended: a) Devices should be handled on benches with conductive and grounded surfaces. b) Ground test equipment, tools and operator. c) Do not handle devices by the leads. d) Store devices in conductive foam or carriers. e) Avoid use of plastic, rubber, or silk in MOS areas. f) Maintain relative humidity above 50 percent if practical. 42 TS68040 2116A-HIREL-09/02 TS68040 Package Mechanical Data 179 pins - PGA Millimeters Dim A B C D E F G H(1) Note: 0.432 Min 46.863 46.863 2.3876 4.318 1.143 1.143 2.54 BSC 0.483 Max 47.625 47.625 1.875 4.826 1.4 1.4 Min 1.845 1.845 0.094 0.170 0.045 0.045 Inches Max 1.875 1.875 0.116 0.190 0.055 0.055 0.100 BSC 0.017 0.019 1. For untinned leads (gold) 43 2116A-HIREL-09/02 196 pins - Tie Bar CQFP Cavity Up (on request) Dim A B C D1 J L Millimeters 3.30 max 0.23 +0.05 0.23 -0.038 0.635 typ. 33.91 0.25 0.89 0.13 63.5 0.51 Inches 0.130 max 0.009 +0.002 0.009 -0.015 .025 typ. 1.335 0.01 0.035 0.005 2.5 0.02 44 TS68040 2116A-HIREL-09/02 TS68040 196 pins - Gullwing CQFP cavity up * Reduce pin count shown for clarity, 49 pins per side Symbol A A1 b Millimeters 4.19 max 0.673 0.2 0.23 +0.05 0.23 -0.038 0.127 +0.05 c 0.127 -0.025 D/E e e1 HD/HE L N R R1 33.91 0.25 .635 BSC 30.48 0.13 38.8 0.18 0.813 0.2 196 0.55 0.25 0.23 min .005 -.001 1.335 .01 .025 BSC 1.2 .005 1.528 .007 .032 .008 196 .022 .01 .009 min Inches 0.165 max .0265 .008 .009 +.002 .009 -.0015 .005 +.002 45 2116A-HIREL-09/02 Ordering Information MIL-STD-883 C and Internal Standard TS68040 M R 1 B/C 25 A Device Revision level Operating frequency: 25: 25 MHz 33: 33 MHz Screening level: B/C: MIL-STD-883, class B D/T: Internal standard with burn-in U: Upscreening U/T: Upscreening + burn-in ___: Internal standard Lead finish: 1: Hot solder dip(1) __: Gold(2) Temperature range: M: Tc = -55; Tj = +125C V: Tc = -40; Tj = +110C Package: F: CQFP/Gullwing leads R: PGA FT: CQFP Flat tie-bar(3) Standard lead finish Gold Gold Gold Notes: 1. On request. 2. Standard process. 3. Non request for small quantity. DESC Drawing 5962-93143 TS68040 DESC 01 X A A Device Revision level DESC Screening Lead finish: A: Hot solder dip C: Gold Speed: 01: 25 MHz 02: 33 MHz Package: X: PGA Y: CQFP Flat tie-bar Z: CQFP Gullwing leads 46 TS68040 2116A-HIREL-09/02 TS68040 Detailed TS68040 Part List Hi-REL Product Commercial Atmel Part Number TS68040MRB/C25A TS68040MRB/C33A TS68040MFB/C25A TS68040MFB/C33A TS68040DESC01XAA TS68040DESC02XAA TS68040DESC01XCA TS68040DESC02XCA TS68040DESC01YCA TS68040DESC02YCA TS68040DESC01ZAA TS68040DESC01ZCA TS68040DESC02ZAA TS68040DESC02ZCA TS68040MFB/C25A TS68040MFB/C33A TS68040MRD/T25A TS68040MRD/T33A TS68040MFD/T25A TS68040MFD/T33A Norms MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 DESC DESC DESC DESC DESC DESC DESC DESC DESC DESC MIL-STD-883 MIL-STD-883 BURN IN BURN IN BURN IN BURN IN Package PGA 179 PGA 179 CQFP 196 CQFP 196 PGA 179 tin PGA 179 tin PGA 179 gold PGA 179 gold CQFP 196 tie bar gold CQFP 196 tie bar gold CQFP 196 gullwing tin CQFP 196 gullwing gold CQFP 196 gullwing tin CQFP 196 gullwing gold CQFP 196 CQFP 196 PGA 179 PGA 179 CQFP 196 CQFP 196 Temperature range (C) TC = -55/+TJ = +125 TC = -55/+TJ = +125 TC = -55/+TJ = +125 TC = -55/+TJ = +125 TC = -55/+TJ = +125 TC = -55/+TJ = +125 TC = -55/+TJ = +125 TC = -55/+TJ = +125 TC = -55/+TJ = +125 TC = -55/+TJ = +125 TC = -55/+TJ = +125 TC = -55/+TJ = +125 TC = -55/+TJ = +125 TC = -55/+TJ = +125 TC = -55/+TJ = +125 TC = -55/+TJ = +125 TC = -55/+TJ = +125 TC = -55/+TJ = +125 TC = -55/+TJ = +125 TC = -55/+TJ = +125 Frequency (MHz) 25 33 25 33 25 33 25 33 25 33 25 25 33 33 25 33 25 33 25 33 Drawing number Atmel datasheet Atmel datasheet Atmel datasheet Atmel datasheet 5962-9314301MXA 5962-9314302MXA 5962-9314301MXC 5962-9314302MXC 5962-9314301MYC 5962-9314302MYC 5962-9314301MZA 5962-9314301MZC 5962-9314302MZA 5962-9314302MZC Atmel datasheet Atmel datasheet Atmel datasheet Atmel datasheet Atmel datasheet Atmel datasheet 47 2116A-HIREL-09/02 Standard Product Commercial Atmel Part Number TS68040VR25A TS68040VR33A TS68040MR25A TS68040MR33A TS68040VF25A TS68040VF33A TS68040MF25A TS68040MF33A Note: Norms Atmel standard Atmel standard Atmel standard Atmel standard Atmel standard Atmel standard Atmel standard Atmel standard Package PGA 179 PGA 179 PGA 179 PGA 179 CQFP 196 CQFP 196 CQFP 196 CQFP 196 Temperature Range (C) TC = -40/+TJ = +110 TC = -40/+TJ = +110 TC = -55/+TJ = +125 TC = -55/+TJ = +125 TC = -40/+TJ = +110 TC = -40/+TJ = +110 TC = -55/+TJ = +125 TC = -55/+TJ = +125 Frequency (MHz) 25 33 25 33 25 33 25 33 Drawing Number Atmel datasheet Atmel datasheet Atmel datasheet Atmel datasheet Atmel datasheet Atmel datasheet Atmel datasheet Atmel datasheet FT: available on request. 48 TS68040 2116A-HIREL-09/02 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France TEL (33) 2-40-18-18-18 FAX (33) 2-40-18-19-60 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France TEL (33) 4-76-58-30-00 FAX (33) 4-76-58-34-80 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France TEL (33) 4-42-53-60-00 FAX (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL 1(719) 576-3300 FAX 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland TEL (44) 1355-803-000 FAX (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 literature@atmel.com Web Site http://www.atmel.com (c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the trademarks of Atmel. UNIX (R) is a Registered Trademark of AT&T Bell Laboratories. Other terms and product names may be the trademarks of others. Printed on recycled paper. 2116A-HIREL-09/02 0M |
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